The design of a typical computer system requires the establishment of a fixed number of addressable registers such as general purpose registers (GPR's) for the programmer to use in designing programs for the machine. Changing the number of architecturally available GPR's once a system is available would require substantial rewriting of programs to make use of the new number of GPR's.
Similarly, the design of computers and computer programs is based on the assumption that computer program instructions are executed by the computer in the order in which they are written and entered into the system. While instructions must logically appear to the computer system to have been executed in sequence, it has been learned in an effort to improve computer performance that some instructions do not have to be physically performed in sequence, provided that certain dependencies do not exist with other instructions. Further, if some instructions are executed out of order, and such an instruction is a branch instruction, where a branch prediction is made to select the instruction sequence, a need to restore the involved register to original values can occur if a wrong branch is predicted. In such a case the system is restored to the point where the branch is taken. The process of executing an instruction out of order efficiently requires that an established or old value be maintained for GPR's affected by the instruction while provision is made to contingently receive new values for the affected GPR's. The contingency is removed and the new value becomes the established value for the GPR's when intervening instructions have completed and branch instructions are resolved.
Large processors have for many years employed overlapping techniques under which multiple instructions are in various states of execution at the same time. Whenever such a technique is employed, it carries with it a need to implement control logic which detects dependencies between instructions and is able to alter the usual overlapped operation so that the results achieved are those described by the "one instruction at a time" architectural model. There are many different forms which overlapping can take, and each one has its own unique set of control problems.
A common form of overlapping is what is called pipelining. Oversimplified, a pipelined machine provides separate hardware for different stages of an instruction's processing. When an instruction finishes its processing at one stage, it moves to the next stage, and the following instruction may move into the stage just vacated. In such a machine, the instructions are kept in sequence with regard to any particular stage of their processing, even though different stages of processing for different instructions are occurring at the same time. In such a processor if the controls detect that a result which has not yet been generated is needed by some other instruction, then the controls must stop part of the pipeline until the result is generated and passed back to where it is needed. Although this control logic can at times be complex, the fact that instructions are kept in sequence in the pipeline is of definite help in keeping the complexity under control.
A more complex form of overlapping occurs if the processor includes separate execution units. Although less common, this technique has also been known and used for many years. Because different instructions have different execution times, and because the inter instruction dependencies will be variable, it is almost inevitable in such a processor that instructions will execute and produce their results in a sequence different from their sequence in the program. Keeping such a processor operating in a logically correct way requires a more complex control mechanism than that for the pipeline organization.
However, multiple execution units in the prior art do not allow precise interruptions to be taken at an arbitrary point. For example, if an instruction creates an overflow condition, by the time this is detected, it is entirely possible that a later instruction in the program is already executed and the result placed in a register or in main storage. This makes it impossible to take an interruption and preserve status of the processor with all prior but no subsequent instructions having executed. In this example, the overflow interrupt will actually be recognized later than it occurred. Other similar situations are possible in the prior art.
The designers of some prior machines chose to handle this situation by allowing all instructions which were in some state of execution to complete their execution as best they could, and then take an "imprecise" interruption which reported that some instruction in the recent past had an overflow condition. This is a reasonable way to handle interruptions for conditions like overflow where the results will be returned to a programmer who will fix a bug or correct the input data and then rerun the program from the beginning. However, it is an unacceptable way to handle interruptions-like page faults where the system program will take some corrective action and then resume execution from the point of interruption.
Applicant is aware of U.S. Pat. No. 4,574,349 assigned to the same assignee as the present invention, in which additional registers are provided to be associated with each GPR and in which register renaming occurs with use of a pointer value. However, this patent does not solve the problem of precise recovery from interrupts or incorrectly guessed branches during out of sequence execution.
An article in the IBM Technical Disclosure Bulletin, entitled "General Purpose Register Extension", August 1981, pages 1404-1405 shows a system for switching between multiple GPR sets to avoid use of storage when switching subroutines. Another article in the IBM Technical Disclosure Bulletin, entitled "Vector-Register Rename Mechanism", June 1982, pages 86-87 shows the use of a dummy register during instruction execution. When execution is complete the register is renamed as the register named by the instruction for receiving results. During execution, the register is transparent and this allows for extra physical registers. However, neither of these articles deals with out-of-sequence instruction execution.
An article in the IBM Technical Disclosure Bulletin, entitled "Use of A Second Set of General Purpose Registers to Allow Changing General-Purpose Registers During Conditional Branch Resolutions", August 1986, pages 991-993 shows a one-for-one matched secondary set of GPRs to hold the original GPR contents during conditional branch resolution and restore the system status if necessary. Conditional mode tags are used with the GPRs to regulate status of the registers or to restore the original contents of the register.